This application is based upon and claims priority of Japanese Patent Applications No. 2001-203723, filed in Jul. 4, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to a semiconductor device and, more particularly, to a semiconductor device having a multilayer interconnection structure, and a manufacturing method thereof.
As semiconductor integrated circuit devices have been becoming smaller in size, a multitude of semiconductor elements have come to be formed on a semiconductor substrate. A single interconnection layer is not sufficient to connect these numerous semiconductor elements. Accordingly, a multilayer interconnection structure laminated in a plurality of interconnection layers is used instead of such a single interconnection layer. A typical multilayer interconnection structure comprises a lamination of a multitude of interconnection layers each formed between insulating interlayer films. In this structure, the interconnection layers are connected by via holes formed in the insulating interlayer films.
Additionally, this multilayer interconnection structure has considerably complicated interconnection patterns corresponding to a multitude of semiconductor elements formed on a substrate. Accordingly, these interconnection patterns have a very large total length. As a result, the delay of an electric signal being transmitted through the interconnection patterns has become too large to ignore, and due to this signal delay, signal waveforms have been broken to a degree that cannot be disregarded. Thereupon, in order to minimize the signal delay in the multilayer interconnection structure, conventional technologies have attempted to use a low dielectric constant material as the insulating interlayer film. Also, in order to minimize an interconnect resistance, conventional technologies have attempted to use a low resistance material, especially Cu, as an interconnect material.
When Cu is used as the interconnect material, a damascene method has been employed, because an effective dry etching method has not been available yet. In the damascene method, grooves corresponding to interconnection patterns and via holes are formed beforehand in an insulating interlayer film; then, the grooves are filled with a Cu layer; and thereafter, part of the Cu layers existing on the surface of the insulating interlayer film is removed by a CMP (Chemical Mechanical Polishing) method.
2. Description of the Related Art
FIG. 1A to FIG. 3B show a first conventional example of steps of forming a multilayer interconnection structure according to a dual damascene method.
In a step shown in FIG. 1A, an underlying interconnection pattern 10, such as Cu, is formed on an Si substrate 1 with an insulating film (not shown in FIG. 1A to FIG. 3B) therebetween. A first etching stopper film 12 of SiN is formed on the underlying interconnection pattern 10 by a plasma CVD method. A first insulating interlayer film 14 of SiO2 is formed on the SiN film 12 by the plasma CVD method. A second etching stopper film 16 of SiN is formed on the SiO2 film 14 by the plasma CVD method. Further, a resist pattern 18 is formed on the SiN film 16. A resist opening 18A is formed in the resist pattern 18 at a position corresponding to a contact hole (28) to be formed in the multilayer interconnection structure.
Next, in a step shown in FIG. 1B, the SiN film 16 is subjected to a dry etching using the resist pattern 18 as a mask so as to form an opening 20 in the SiN film 16. The opening 20 is formed at a position corresponding to the resist opening 18A. After the opening 20 is formed, the resist pattern 18 is removed by ashing.
Next, in a step shown in FIG. 1C, an SiO2 film 22 is so formed, as a second insulating interlayer film, on the SiN film 16 by a CVD method as to cover the opening 20.
Subsequently, in a step shown in FIG. 2A, a resist pattern 24 having an opening 24A is formed on the SiO2 film 22. The opening 24A is at a position corresponding to an interconnection groove (26) to be formed in the SiO2 film 22 so as to include the opening 20 formed in the SiN film 16. In a step shown in FIG. 2B, the SiO2 film 22 is subjected to a dry etching using the resist pattern 24 as a mask so as to form an interconnection groove 26 in the SiO2 film 22. At this point, the SiN film 16 and the opening 20 are exposed at the bottom of the interconnection groove 26. The above-mentioned dry etching is continuously performed to the Sio2 film 14 exposed in the opening 20 by using the SiN film 16 as a mask so as to form a contact hole 28 in the SiO2 film 14. The SiN film 12 is exposed at the bottom of the contact hole 28.
Subsequently, in a step shown in FIG. 2C, the SiN film 12 exposed at the bottom of the contact hole 28 is removed by etching so that the Cu interconnection pattern 10 is exposed at the bottom of the contact hole 28. In a step shown in FIG. 3A, the interconnection groove 26 and the contact hole 28 are filled by sputtering Cu and electroplated Cu. Further, in a step shown in FIG. 3B, a part of the Cu layer 29 above the surface of the second insulating interlayer film 22 is removed by a CMP method so as to leave a Cu pattern 29A in the interconnection groove 26 and the contact hole 28 of the multilayer interconnection structure shown in FIG. 3B.
In the above-described steps of forming the multilayer interconnection structure according to the dual damascene method, the interconnection groove 26 and the contact hole 28 are continuously formed by one dry etching process. This simplifies manufacturing steps of a semiconductor device.
FIG. 4A to FIG. 5C show a second conventional example of steps of forming a multilayer interconnection structure. Elements in FIG. 4A to FIG. 5C that are described above are referenced by the same reference marks, and will not be described in detail.
In a step shown in FIG. 4A, an SiN film 30 is formed, as a first etching stopper film, on the Cu interconnection pattern 10 by a plasma CVD method. In this second example, an organic SOG film 32 is applied, as a first insulating interlayer film, on the SiN film 30 by such a method as a spin coating. An SiN film 34 is formed, as a second etching stopper film, on the organic SOG film 32 by the plasma CVD method. Further, an organic SOG film 36 is formed, as a second insulating interlayer film, on the SiN film 34 by the plasma CVD method.
Further, a resist pattern 38 having an opening 38A is formed on the organic SOG film 36. The opening 38A is at a position corresponding to a contact hole (40) to be formed in the organic SOG film 32.
Next, in a step shown in FIG. 4B, the organic SOG film 36, the SiN film 34 and the organic SOG film 32 are etched by using the resist patter 38 as a mask so as to form a contact hole 40.
Subsequently, in a step shown in FIG. 4C, a resist pattern 42 having an opening 42A is formed on the organic SOG film 36. The opening 42A is at a position corresponding to an interconnection groove (44) to be formed in the organic SOG film 36 so as to include the contact hole 40.
Subsequently, in a step shown in FIG. 5A, the organic SOG film 36 is etched by using the resist pattern 42 as a mask so as to form an interconnection groove 44 in the organic SOG film 36. During this interconnection groove 44 being formed, the resist pattern 42 is removed by the organic SOG film 36 etching. As described above, the interconnection groove 44 includes the contact hole 40. The interconnection groove 44 exposes the SiN film 34 at the bottom part thereof. The contact hole 40 exposes the SiN film 30 at the bottom thereof.
After the etching process in the step shown in FIG. 5A, a step shown in FIG. 5B is performed, in which the SiN film 34 exposed at the bottom part of the interconnection groove 44 and the SiN film 30 exposed at the bottom of the contact hole 40 are etched such that the underlying Cu interconnection pattern 10 is exposed at the bottom of the contact hole 40. In a step shown in FIG. 5C, the interconnection groove 44 and the contact hole 40 are filled with the Cu layer 29, as in the step shown in FIG. 3A. Further, in the step shown in FIG. 5C, a part of the Cu layer 29 above the surface of the second insulating interlayer film 36 is removed by a CMP method, as in the step shown in FIG. 3B, so as to leave the Cu pattern 29A in the interconnection groove 44 and the contact hole 40 of the multilayer interconnection structure.
As described above, in a dual damascene process according to the second conventional example, the contact hole 40 and the interconnection groove 44 are formed by two separate etching processes. This facilitates an alignment of a mask in a resist patterning for the interconnection groove.
The organic insulating interlayer films 32 and 36 used in the above-described steps shown in FIG. 4A to FIG. 5C can be applied to the steps of forming the insulating interlayer films shown in FIG. 1A to FIG. 3B. Conversely, the inorganic insulating interlayer films 14 and 22 used in the above-described steps shown in FIG. 1A to FIG. 3B can be applied to the steps of forming the insulating interlayer films shown in FIG. 4A to FIG. 5C.
The actual multilayer interconnection structure includes a plurality of the structures each shown in FIG. 3B or FIG. 5C by repeating the steps shown in FIG. 1A to FIG. 3B or the steps shown in FIG. 4A to FIG. 5C.
As described above, the etching stopper films 12 and 16 or the etching stopper films 30 and 34 play an important role in forming a multilayer interconnection structure according to a dual damascene method. Conventionally, SiN films have been used as these etching stopper films, because the SiN films can secure a large etching selectivity in contrast to the insulating interlayer films.
By the way, in order that the SiN films function as effective etching stopper films, the SiN films need to have a large film density. Therefore, in general, the SiN films are formed by a plasma CVD method at a high temperature not lower than 400xc2x0 C. However, when the SiN films are formed at such a high temperature, a thermal expansion occurs in a Cu interconnection pattern already formed in an interconnection structure; thereafter, when the temperature is returned to a room temperature, a large residual stress occurs in the Cu interconnection pattern. The SiN film formed on the Cu interconnection pattern functions not only as an etching stopper film, but also as a diffusion prevention film preventing the diffusion of Cu.
In the interconnection structure including the Cu interconnection pattern subjected to the residual stress, especially when the interconnection structure is left in a high-temperature environment, a stress-migration tends to occur in the Cu interconnection pattern, causing a reliability problem such as a disconnection of the Cu interconnection pattern. Further, when the SiN films are formed at a high temperature, a Cu protuberance tends to occur in an interface between the Cu interconnection pattern and the SiN film. The problem of the above-mentioned stress-migration in the Cu interconnection pattern has been becoming serious in a recent micronized semiconductor device.
FIG. 6 shows an example of a semiconductor device in which a stress-migration occurs in a Cu interconnection pattern.
As shown in FIG. 6, an n-type well 51A and a p-type well 51B are formed according to element areas isolated by an isolation area 52 on an Si substrate 51. In the element area comprising the n-type well 51A, a gate electrode 53A is formed on the surface of the Si substrate 51 with a gate oxide film therebetween. Similarly, in the element area comprising the p-type well 51B, a gate electrode 53B is formed on the surface of the Si substrate 51 with a gate oxide film therebetween. In the n-type well 51A, p-type diffusion areas 51a and 51b are formed at both sides of the gate electrode 53A. Similarly, in the p-type well 51B, n-type diffusion areas 51c and 51d are formed at both sides of the gate electrode 53B.
An insulating interlayer film 54 is so formed on the Si substrate 51 as to cover the gate electrodes 53A and 53B. Via holes 54a to 54d are formed in the insulating interlayer film 54 by using an SiN film 55 formed thereon as a mask so as to expose the diffusion areas 51a to 51d on the bottom. W-plugs 54A to 54D are formed in the via holes 54a to 54d. 
An interconnection layer 56 is formed on the SiN film 55. The interconnection layer 56 includes Cu interconnection patterns 56A to 56D contacting the W-plugs 54A to 54D, respectively. An insulating interlayer film 58 is formed on the interconnection layer 56 with an etching stopper film 57 therebetween. The etching stopper film 57 is formed by an SiN film.
Via holes 59A to 59C are formed in the insulating interlayer film 58 by using an SiN film 59 formed thereon as a mask. The via holes 59A to 59C are formed at positions corresponding to the Cu interconnection patterns 56A to 56C, respectively. In a state shown in FIG. 6, the via holes 59A to 59C reach the SiN etching stopper film 57.
In the semiconductor device shown in FIG. 6, when the SiN film 57 is formed at a normal processing temperature of approximately 400xc2x0 C., stress-migrations occur in the Cu interconnection patterns 56A to 56D in the interconnection layer 56 due to a residual stress, or Cu protuberances occur in interfaces between the Cu interconnection patterns 56A to 56D and the SiN film 57, as described above. As a result, the SiN etching stopper film 57 may possibly be damaged, as seen in the via hole 59B shown in FIG. 6. When the etching stopper film 57 is damaged as in the via hole 59B, the Cu interconnection pattern 56B thereunder is exposed so as to cause a problem such as a disconnection in the Cu interconnection pattern 56B. Such defects in the Cu interconnection patterns due to stress-migrations and Cu protuberances are likely to occur when the semiconductor device is left in a high-temperature environment.
In order to relax the residual stress occurring in the Cu interconnection patterns, the SiN film may be formed at a lower temperature. However, an SiN film formed at such a low temperature has a low film density, and thus does not function as an effective etching stopper film in forming a contact hole and an interconnection groove. As a result, using such an SiN film formed at a low temperature as the etching stopper film 57 decreases an initial yield in manufacturing a semiconductor device.
By the way, conventionally, as seen in Japanese Laid-Open Patent Application No. 2000-183059, there has been a publicly known structure for increasing an adhesion between the Cu interconnection pattern and the SiN etching stopper film, in which an Si-rich SiN film is used as an etching stopper film at a part contacting a Cu interconnection pattern, and an N-rich SiN film is formed on the Si-rich SiN film. According to this publicly known method, these SiN films can be formed at a temperature not higher than 400xc2x0 C. Therefore, it is conceivable that this method can possibly solve the above-mentioned problem of the stress-migration in the Cu interconnection pattern.
However, when an experiment is actually carried out in which the Si-rich SiN film is so formed as to contact the Cu interconnection pattern, there occurs a problem that SiH4 abundantly supplied as a substance for the Si-rich SiN film reacts with the Cu interconnection pattern so that a high-resistive Cu-silicide (CuSi2) is formed on the surface of the Cu interconnection pattern. Accordingly, it is confirmed that the above-mentioned conventional method cannot solve the problem of the stress-migration in a multilayer interconnection structure including a Cu interconnection pattern.
It is a general object of the present invention to provide an improved and useful semiconductor device and a manufacturing method thereof in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to alleviate a stress-migration occurring in a Cu interconnection pattern included in a multilayer interconnection structure of a semiconductor device.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a method of manufacturing a semiconductor device, the method comprising the steps of:
forming an insulating interlayer film on a substrate;
forming a Cu interconnection pattern in the insulating interlayer film;
forming a first insulating film on the insulating interlayer film at a first temperature lower than 400xc2x0 C. in a nonoxide situation so that the first insulating film covers the Cu interconnection pattern; and
forming a second insulating film on the first insulating film at a second temperature higher than the first temperature.
Additionally, the semiconductor device manufacturing method according to the present invention may preferably further comprise the temperature-decreasing step of decrease a substrate temperature from the first temperature to a room temperature, and the temperature-increasing step of increase the substrate temperature from the room temperature to the second temperature, after the step of forming the first insulating film and before the step of forming the second insulating film.
Additionally, in the semiconductor device manufacturing method according to the present invention, the step of forming the first insulating film, the temperature-decreasing step, the temperature-increasing step and the step of forming the second insulating film may preferably be performed in succession in a same depositing device.
Additionally, in the semiconductor device manufacturing method according to the present invention, when the first insulating film and the second insulating film are SiN films, the step of forming the first insulating film may preferably be performed by setting the first temperature within a range from 300 to 350xc2x0 C., and the step of forming the second insulating film may preferably be performed by setting the second temperature within a range from 350 to 400xc2x0 C. Additionally, the step of forming the first insulating film and the step of forming the second insulating film may preferably be performed by a plasma CVD method in a mixed gas plasma of a silane gas, an ammonia gas and a nitrogen gas.
Additionally, in the semiconductor device manufacturing method according to the present invention, when the first insulating film and the second insulating film are SiN films, the step of forming the first insulating film may preferably be performed by setting the first temperature within a range from 300 to 350xc2x0 C., and the step of forming the second insulating film may preferably be performed by setting the second temperature within a range from 350 to 400xc2x0 C. Additionally, the step of forming the first insulating film and the step of forming the second insulating film may preferably be performed by a plasma CVD method in a mixed gas plasma of a methylsilane gas, an ammonia gas and a nitrogen gas.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a semiconductor device comprising:
a substrate;
a first insulating interlayer film formed on the substrate;
a Cu interconnection pattern formed in the first insulating interlayer film;
a first insulating film formed on the first insulating interlayer film so as to cover the Cu interconnection pattern and contact the Cu interconnection pattern, the first insulating film being composed of a nonoxide;
a second insulating film formed on the first insulating film; and
a second insulating interlayer film formed on the second insulating film,
wherein the second insulating film exhibits a lower etching rate when an etching process is performed to the second insulating interlayer film than an etching rate of the first insulating film when the etching process is performed to the first insulating film.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a semiconductor device comprising:
a substrate;
an insulating interlayer film formed on the substrate;
a Cu interconnection pattern formed in the insulating interlayer film;
a first insulating film formed on the insulating interlayer film so as to cover the Cu interconnection pattern and contact the Cu interconnection pattern, the first insulating film being composed of a nonoxide; and
a second insulating film formed on the first insulating film,
wherein the second insulating film has a higher film density than the first insulating film.
Additionally, in the semiconductor device according to the present invention, the first insulating film and the second insulating film may preferably be formed of SiN films or SiC films. When the first insulating film and the second insulating film are formed of SiN films, the first insulating film may preferably be so formed as to have a film density lower than 2.8 g/cm3, and the second insulating film may preferably be so formed as to have a film density equal to or higher than 2.8 g/cm3. When the first insulating film and the second insulating film are formed of SiC films, the first insulating film may preferably be so formed as to have a film density lower than 1.9 g/cm3, and the second insulating film may preferably be so formed as to have a film density equal to or higher than 1.9 g/cm3.
According to the present invention, the first insulating film directly covering the Cu interconnection pattern is formed at a low temperature so as to avoid a problem of a residual stress occurring in the Cu interconnection pattern and a stress-migration resulting therefrom. On the other hand, when the first insulating film is formed at such a low temperature as to prevent a stress-migration, the first insulating film may possibly come to have too low a film density to function sufficiently as an etching stopper film. To avoid this risk, the second insulating film having a high film density is formed on the first insulating film at a higher temperature. When the second insulating film is formed at such a high temperature, the Cu interconnection pattern undergoes a high-temperature treatment. However, the first insulating film already formed on the surface of the Cu interconnection pattern can restrain the above-mentioned stress-migration.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.